1. Field of the Invention
The present invention relates to an insulated gate semiconductor device, and particularly to an insulated gate semiconductor device capable of reducing a region where no transistor cells can be provided (hereinafter, a region where no transistor is (can be) formed) and thereby increasing an area of a diode region.
2. Description of the Related Art
In an insulated gate semiconductor device, a source electrode layer and a gate electrode layer are formed on a principal surface of a substrate. In addition, external connection means such as a bump electrode and a bonding wire is bonded to each of the source electrode layer and the gate electrode layer.
In addition, there has been known an insulated gate semiconductor device in which an electrode on a surface of a substrate has a two-layer structure so as to reduce resistance in an electrode portion.
A conventional insulated gate semiconductor device 200 that has the two-layer electrode structure will be described by referring to FIG. 10. The description that follows is based on an example of a MOSFET. FIG. 10 is a sectional view.
MOSFET transistor cells 225 (referred to as cells below) are formed in a device region 220.
Each of the cells 225 is formed in a p type channel layer 204 formed on a surface of an n− type epitaxial layer 202 which is formed on an n+ type silicon semiconductor substrate 201 and serves as a drain region of the cell 225. Trenches 208 are formed to penetrate the channel layer 204. A gate oxide film 211 is formed on an internal wall of each of the trenches 208. A gate electrode 213 is buried in each trench 208. Each of the gate electrodes 213 is connected to a first gate electrode layer 218 and further to a protection diode Di via a connection portion (not illustrated in FIG. 10) that is formed by patterning polysilicon.
Source regions 215 are diffusion regions each formed by implanting n+ type impurities in a portion, adjacent to the trench 208, in a surface of the channel layer 204. In addition, body regions 214, which are diffusion regions of p+ type impurities, are each provided in a portion, between two adjacent ones of the source regions 215, in a surface of the channel layer 204. Interlayer insulating films 216 are formed respectively on the gate electrodes 213. Contact holes are formed between the interlayer insulating films 216. A first source electrode layer 217 is in contact with the source regions 215 and the body regions 214 via the contact holes.
The first gate electrode layer 218 is provided over the protection diode Di, and is connected to a first end portion of the protection diode Di. The first end portion of the protection diode Di is thus connected to the gate electrodes 213. A second end portion of the protection diode Di is connected to the first source electrode layer 217.
The first source electrode layer 217 is formed to cover the entire area of the device region 220, and is connected to the source regions 215 and the body regions 214 of the cells 225. The first gate electrode layer 218 is formed above a portion of the substrate surface located outside the device region 220.
A second source electrode layer 227 and a second gate electrode layer 228 are formed to reduce the resistance in the electrode portions. A nitride film 221, for example, is formed to cover a part of the surface of the first source electrode layer 217. Then, the second source electrode layer 227 is formed to cover the first source electrode layer 217 and the nitride film 221. The second source electrode layer 227 thus formed is allowed to be in contact with the first source electrode layer 217. Meanwhile, another nitride film 221, for example, is formed to cover the first gate electrode layer 218. Then, the second gate electrode layer 228 is formed to cover the first gate electrode layer 218 and this nitride film 221. The second gate electrode layer 228 thus formed is allowed to be in contact with the first gate electrode layer 218.
A nitride film 223, which is to serve as the outermost surface of the chip, is formed on the second source electrode layer 227 and the second gate electrode layer 228. Opening portions are formed in the nitride film 223. A portion of the second gate electrode layer 228 is thus exposed outside through the opening, and the exposed portion serves as a region where external connection means is bonded (hereafter, the portion will be referred to as a “gate pad portion 228p”). Likewise, a portion of the second source electrode layer 227 is thus exposed outside through the opening, and the exposed portion serves as a region where external connection means is bonded (hereafter, the portion will be referred to as a “source pad portion 227p”). The nitride films 221 are formed below the gate pad portion 228p and the source pad portion 227p, and function to soften the impact caused by wire bonding (this technology is described for instance in Japanese Patent Application Publication No. 2007-42817).
FIGS. 11A and 11B are plan views illustrating an example of conventional semiconductor chips (denoted by 210 in FIG. 11A). Note that the semiconductor chip shown in this example uses bump electrodes as external connection means and is thus mounted on a packaging substrate by the flip-chip technique. In addition, in the semiconductor chip shown in this example, two MOSFET-device regions are integrated in a single substrate (chip) while the two MOSFETs share a single common drain region (hereafter, a semiconductor chip of this type will be referred to as a “common-drain MOSFET”). Note that if those constituent elements shown in FIGS. 11A and 11B are the same ones that are shown in FIG. 10, the reference numerals used in FIG. 10 are also used to denote the constituent elements in FIGS. 11A and 11B.
The common-drain MOSFET 210 includes two gate pad portions 228p, 228p′ and two source pad portions 227p, 227p on a principal surface of the substrate (chip). Gate bump electrodes 238, 238′ and source bump electrodes 237, 237′ are formed as the external connection means respectively for the pad portions 228p, 228p′, 227p, and 227p′. A current flows from the source bump electrode 237 through the common drain region to the source bump electrode 237′.
A protection diode Di smaller than the gate pad portion 228p is formed below the gate pad portion 228p to overlap the gate pad portion 228p. A first end portion of the protection diode Di is connected to the first gate electrode layer 218, while a second end portion of the protection diode is connected to the first source electrode layer 217 (see FIG. 10). The first gate electrode layer 218 extends to form a gate extraction electrode 218w formed in the peripheral portion of the substrate, and is thus connected further to the gate electrode (not illustrated).
As FIGS. 11 to 12B show, the first gate electrode layer 218 is formed below the gate pad portion 228p to overlap and contact the gate pad portion 228p. Below the first gate electrode layer 218, the protection diode Di is provided between the gate and the source. The gate pad portion 228p, the first gate electrode layer 218, and the protection diode Di overlap one another. The protection diode Di is formed to have a smaller area than the area covered by the gate pad portion 228p (see FIGS. 11A and 11B).
The protection diode Di is formed on an insulating layer formed on the substrate surface. The protection diode Di is formed by patterning polysilicon into a desired shape. Accordingly, for reasons associated with the structure or with the manufacturing processes of the protection diode Di, neither the first source electrode layer 217 nor the transistor cells covered by and connected to the first source electrode layer 217 can be provided below the protection diode Di. Consequently, cells are provided in the device region 220 indicated by the dashed lines in FIG. 11.
In addition, the gate pad portion 228p and the protection diode Di overlap each other, and are located at the inner side of the device region 220 than the outermost cells of the device region 220. Accordingly, for connecting the gate extraction electrode 218w, which is the first layer located in the peripheral portion of the chip, to the gate pad portion 228p, a wiring portion 228w has to be formed as the first layer. In addition, a wiring portion of the polysilicon layer which overlaps the wiring portion 228w and which is connected to the protection diode Di is also provided below the wiring portion 228w. Accordingly, neither the first source electrode layer 217 nor the cells can be provided below the wiring portion 228w. 
The gate pad portion 228p occupies at least an area having a side (diameter) of several tens of micrometers approximately if such means as bonding wires are employed as external connection means. If bump electrodes are employed instead of the bonding wires, the gate pad portion 228p sometimes occupies an area having a side (diameter) of 300 μm or even larger.
The area that the protection diode Di occupies is determined depending upon the breakdown voltage. A sufficiently high breakdown voltage is often obtainable even if the area of the protection diode Di is smaller than the area of the gate pad portion 228p. FIG. 11B illustrates the protection diode Di so that the area of the protection diode Di is approximately equal to the area of the gate pad portion 228p and to the area of the first gate electrode layer 218. In practice, however, the polysilicon layer is formed to have an area approximately equal to the area of the gate pad portion 228p and to the area of the first gate electrode layer 218, while the protection diode Di is formed in the polysilicon layer to have an area smaller than the area of the gate pad portion 228p and to the area of the first gate electrode layer 218.
In conventional cases, however, the protection diode Di is formed below the gate pad portion 228p so that the protection diode Di and the gate pad portion 228p overlap each other. Accordingly, the semiconductor device has a structure that does not allow transistor cells to be provided below the gate pad portion 228p. Consequently, a larger area has to be left as the region where no transistor is (can be) formed that does not substantially function as the device region. Such a structure restricts improvement in the characteristics of the semiconductor device.
Suppose a case where the protection diode Di may have a smaller area that depends on the required breakdown voltage and the protection diode Di is formed to have a smaller area than the area of the gate pad portion 228p. Even in this case, no transistor cells can be provided below the gate pad portion 228p. 
In a conventional structure, no cells are provided below the gate pad portion 228p, but are provided in the area surrounding the gate pad portion 228p. A semiconductor device having the conventional structure has another problem of the difficulty in accomplishing uniform operations of the cells. Specifically, the first source electrode layer 217 and the second source electrode layer 227 (since the two source electrode layers 217 and 227 have the same patterns, the two source layers 217 and 227 will be referred to, by use of a generic term, as the “source electrode layers”) are patterned in areas not including the region where the gate pad portion 228p is to be provided. Accordingly, in a region far from the source pad portion 22′7p, the current flowing in each of the source electrode layers in a horizontal direction with the surface of the substrate flows around the gate pad portion 228p. A problem thus caused is an increase in the resistance within each of the source electrode layers.
The problem occurs not only in the case of semiconductor chips having a flip-chip mounting structure but also in the case of semiconductor chips whose external connection means are provided by wire bonding or metal plates.
FIGS. 11A and 11B are provided to illustrate the case of a common-drain MOSFET. A similar problem occurs in the case of MOSFETs of up-drain structure with the drain electrode extracted out to the same principal surface that the source electrode layer and the gate electrode layer are formed on. In addition, a similar problem occurs also in the case of ordinary MOSFETs with the drain electrode formed on the back-side surface.
Now, the problem will be described in further detail below. The positions of the pad portions within a semiconductor chip are preferably determined according to the characteristics of the semiconductor chip as appropriate. Such positioning, however, is sometimes impossible due to the constraints imposed by the pattern. For example, in the case where bump electrodes 237, 237′, 238, and 238′ are formed, the positions of the bump electrodes 237, 237′, 238, and 238′ are constrained by the pattern formed on the packaging substrate. The positions of the pad portions are determined, for example, according to the user's requirements. Specifically, a larger-sized chip tends to have the bump electrodes positioned closer to the center of the chip rather than in the peripheral portions. For this reason, the source pad portion 227p and the gate pad portion 228p are formed at inner-side positions than the cells located at the outermost positions of the device region 220.
Incidentally, a current pass is formed in the case shown in FIGS. 11A and 11B from the source bump electrode 237 serving as the input terminal to the source bump electrode 237′ serving as the output terminal through the substrate (a shared drain region).
In terms of the pass of the current flow through the source electrode layer of each MOSFET, the current flows from the source pad portion 227p (likewise in the case of the source pad portion 227p′) to end portions of the source electrode layer. Now suppose a case where the gate pad portion 228p is positioned at the inner side than the cells positioned at the outermost positions of the device region 220. In this case, the current flowing through the cells located in the portions surrounding the gate pad portion 228p, in particular, through the cells positioned between the gate pad portion 228p and the end portions of the chip (i.e., positioned in the area indicated by the alternate long and short dash line in FIG. 11A), flows from the source bump electrode 237 going all the way around the gate pad portion 228p. Accordingly, the current flowing through these cells has to pass through a longer pass in the source electrode layer than in the case of the current flowing through the cells positioned near the source pad portion 227p. The resistance in the case of the longer pass is higher than in the case of the shorter pass.
Accordingly, the device region 220 includes both a region where the current pass for the cells is shorter and has lower resistance (i.e., a region in the vicinity of each of the source bump electrodes 237, 237′) and a region where the current pass for the cells is longer and has higher resistance (a region r1 indicated by the alternate long and short dash line in FIG. 11A. The cells of lower resistance perform well, but the cells of higher resistance perform unsatisfactorily. If the gap in the performance of these two groups of cells becomes wider, it is difficult for the cells within the device region to accomplish uniform operation. This causes a problem of deterioration of the switching characteristics.
FIG. 11A shows regions r2 each of which is located in an area between the gate pad portion 228p and an end portion of the device region 220. Each of the region r2 has an area of a smaller width available for the source electrode layer to be placed in the region r2. The cells that the current can reach after passing through the regions r2 have larger resistance, resulting in a problem of difficulty in the uniform operation.
The problem occurs not only in the common-drain MOSFETs but also in the MOSFETs of up-drain structure and of ordinary MOSFETs with the drain electrode foamed on the back-side surface. A similar problem occurs in any MOSFET in which the gate pad portion is formed at the inner side than the outermost transistor cells in the device region and the transistor cells are arranged so that the current flowing through the source electrode layer goes all the way around the gate pad portion.